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<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle">
<div class="title">cy_stc_clkref_csv_manual_config_t Struct Reference<div class="ingroups"><a class="el" href="group__group__sysclk.html">SysClk       (System Clock)</a> &raquo; <a class="el" href="group__group__sysclk__clk__ref__structs.html">Group_sysclk_clk_ref_structs</a></div></div>  </div>
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<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><dl class="section note"><dt>Note</dt><dd>This structure is available for CAT1C devices. </dd></dl>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a257cdeeec0fd60d59b651d83220c18cd"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__clkref__csv__manual__config__t.html#a257cdeeec0fd60d59b651d83220c18cd">startTime</a></td></tr>
<tr class="memdesc:a257cdeeec0fd60d59b651d83220c18cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Startup delay time, after enable or DeepSleep wakeup, from reference clock start to monitored clock start.  <a href="#a257cdeeec0fd60d59b651d83220c18cd">More...</a><br /></td></tr>
<tr class="separator:a257cdeeec0fd60d59b651d83220c18cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a916154388655bc531a1ff1b151909e72"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__clkref__csv__manual__config__t.html#a916154388655bc531a1ff1b151909e72">lowerLimit</a></td></tr>
<tr class="memdesc:a916154388655bc531a1ff1b151909e72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lower limit in reference clock cycles, before the next monitored clock event is allowed to happen.  <a href="#a916154388655bc531a1ff1b151909e72">More...</a><br /></td></tr>
<tr class="separator:a916154388655bc531a1ff1b151909e72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a40f62ec7257a1e7a7fbd402cddf5bfa3"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__clkref__csv__manual__config__t.html#a40f62ec7257a1e7a7fbd402cddf5bfa3">upperLimit</a></td></tr>
<tr class="memdesc:a40f62ec7257a1e7a7fbd402cddf5bfa3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Upper limit in reference clock cycles, before (or same time) the next monitored clock event must happen.  <a href="#a40f62ec7257a1e7a7fbd402cddf5bfa3">More...</a><br /></td></tr>
<tr class="separator:a40f62ec7257a1e7a7fbd402cddf5bfa3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac140228fd8923a334c905e4438803202"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__clkref__csv__manual__config__t.html#ac140228fd8923a334c905e4438803202">period</a></td></tr>
<tr class="memdesc:ac140228fd8923a334c905e4438803202"><td class="mdescLeft">&#160;</td><td class="mdescRight">Period in monitored clock cycles, before the next monitored clock event happens.  <a href="#ac140228fd8923a334c905e4438803202">More...</a><br /></td></tr>
<tr class="separator:ac140228fd8923a334c905e4438803202"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
<a id="a257cdeeec0fd60d59b651d83220c18cd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a257cdeeec0fd60d59b651d83220c18cd">&#9670;&nbsp;</a></span>startTime</h2>

<div class="memitem">
<div class="memproto">
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          <td class="memname">uint32_t cy_stc_clkref_csv_manual_config_t::startTime</td>
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<p>Startup delay time, after enable or DeepSleep wakeup, from reference clock start to monitored clock start. </p>

</div>
</div>
<a id="a916154388655bc531a1ff1b151909e72"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a916154388655bc531a1ff1b151909e72">&#9670;&nbsp;</a></span>lowerLimit</h2>

<div class="memitem">
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          <td class="memname">uint32_t cy_stc_clkref_csv_manual_config_t::lowerLimit</td>
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<p>Lower limit in reference clock cycles, before the next monitored clock event is allowed to happen. </p>

</div>
</div>
<a id="a40f62ec7257a1e7a7fbd402cddf5bfa3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a40f62ec7257a1e7a7fbd402cddf5bfa3">&#9670;&nbsp;</a></span>upperLimit</h2>

<div class="memitem">
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          <td class="memname">uint32_t cy_stc_clkref_csv_manual_config_t::upperLimit</td>
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</div><div class="memdoc">

<p>Upper limit in reference clock cycles, before (or same time) the next monitored clock event must happen. </p>

</div>
</div>
<a id="ac140228fd8923a334c905e4438803202"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ac140228fd8923a334c905e4438803202">&#9670;&nbsp;</a></span>period</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">uint32_t cy_stc_clkref_csv_manual_config_t::period</td>
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<p>Period in monitored clock cycles, before the next monitored clock event happens. </p>

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